This invention relates to data processing systems.
In one form of data processing system which has been proposed, the execution of each program instruction is divided into a number of phases, and each of these phases is performed by a different processing stage of the system, so that the execution of successive instructions can be overlapped. Such a system is referred to as a pipeline processor, since the flow of instructions through the processing stages is analogous to the flow of fluid through a pipeline.
The advantage of a pipeline processor is that it can achieve high processing rates, as a result of the parallel operation of the multiple processing stages. The effective processing speed is determined by the rate at which execution of the instructions can be initiated, rather than by the time required to execute each individual instruction.
However, pipeline processors present considerable problems in synchronising and co-ordinating the operation of the various processing stages, to ensure that all the necessary operations are performed in the correct sequence, and to prevent situations where no stage can proceed further since each is waiting for another to complete some task, or where two stages attempt to access a store or a register simultaneously. This involves a considerable number of specially designed logic circuits, with the result that such systems tend to be very expensive.
One object of the present invention is to provide a novel form of data processing system in which execution of instructions can be overlapped, but which avoids the above mentioned problems.